| 三阶级联Sigma-Delta调制器设计 |
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| 引用本文： | 郭先清,林凡,吴孙桃.三阶级联Sigma-Delta调制器设计[J].微电子学与计算机,2007,24(1):66-68,72. |
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| 作者姓名： | 郭先清 林凡 吴孙桃 |
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| 作者单位： | 1. 厦门大学,物理系,福建,厦门,361005
2. 厦门大学,萨本栋微机电研究中心,福建,厦门,361005 |
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| 摘 要： | 介绍2-1级联的三阶调制器设计结构，讨论信号比例系数、积分增益系数和电路非理想特性对调制器系统的性能影响：运用SIMULINK对调制器建模并仿真，模型中考虑．开关电容积分器的非理想因素对整个调制器的影响．并通过调整信号比例和积分增益系数来确定调制器性能和电路要求。当采样率为125和时钟频率2．50MHz时．该模型结构得到93dB的信噪失真比，可应用于实际的电路系统。
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| 关 键 词： | Sigma-delta调制器 级联结构 非理想因素 |
| 文章编号： | 1000-7180（2007）01-0066-03 |
| 修稿时间： | 2005-11-23 |
Design of Third Order Cascade Sigma-Delta Modulator |
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| GUO Xian-qing,LIN Fan,WU Sun-tao.Design of Third Order Cascade Sigma-Delta Modulator[J].Microelectronics & Computer,2007,24(1):66-68,72. |
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| Authors: | GUO Xian-qing LIN Fan WU Sun-tao |
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| Affiliation: | 1. Department of Physics, Xiamen University, Xiamen 361005, China;2. Pen-Tung Sah MEMS Research Center, Xiamen University, Xiamen 361005, China |
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| Abstract: | This paper describes the architecture techniques which can be employed to enhance the system-level modulator performance. The 2-1 cascaded architecture used in this design is presented, along with a discussion on the integrator gain factors and a consideration of the circuit non-idealities, including signal scaling and capacitor scaling, which affect its performance. With an oversampling ratio of 125 and a clock frequency of 2.5MHz, the modulator achieves a 90dB dynamic range and a peak signal-to-noise distortion ratio (SNDR) of 93dB. |
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| Keywords: | Sigma-delta modulator Cascaded hitecture Non-ideality |
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