| 一种基于电荷泵锁相环的时钟调节电路设计 |
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| 引用本文： | 王雪萍,王金龙,蔡永涛,马金龙. 一种基于电荷泵锁相环的时钟调节电路设计[J]. 中国集成电路, 2021, 0(1) |
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| 作者姓名： | 王雪萍 王金龙 蔡永涛 马金龙 |
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| 作者单位： | 中国电子科技集团公司第58研究所 |
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| 摘 要： | 设计了一种基于电荷泵锁相环(PLL)的独特时钟调节电路,可调节时钟频率和延时,可纠正时钟偏斜,能够输出不同相位(0°,90°,180°,270°)锁定且低抖动的各种频率信号,锁相环可外部动态配置。该电路可应用于FPGA系统集成电路的时钟发生源电路中,能够提供非常灵活的时钟调节功能。仿真结果表明,该电路满足设计需求。
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| 关 键 词： | 电荷泵 锁相环 时钟 FPGA |
A Design of Clock Regulating Circuit Based on Charge Pump Phase Locked Loop |
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| WANG Xue-ping,WANG Jin-long,CAI Yong-tao,MA Jin-long. A Design of Clock Regulating Circuit Based on Charge Pump Phase Locked Loop[J]. China Integrated Circuit, 2021, 0(1) |
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| Authors: | WANG Xue-ping WANG Jin-long CAI Yong-tao MA Jin-long |
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| Affiliation: | (No.58 Research Institute,China Electronics Technology Corporation) |
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| Abstract: | A unique clock adjusting circuit based on charge pump phase-locked loop(PLL)is designed,which can adjust the clock frequency and delay,correct the clock skew,output various frequency signals with different phase locking and low jitter(0°,90°,180°,270°).The PLL can be configured in external dynamic state.The circuit can be used in the clock generator of FPGA system integrated circuit,and can provide very flexible clock adjustment function.The simulation results show that the circuit meets the design requirements. |
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| Keywords: | Charge Pump Phase-locked Loop Clock FPGA |
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