基于时钟网络的高速数据采集与处理系统设计

针对全波形激光雷达中高速率数据采集系统的需求，研制了一种基于时钟网络的高速数据采集与处理系统，对其中的关键技术进行了研究。在对FPGA片同步技术及时钟抖动机理进行分析的基础上，提出一种以锁相环和时钟缓冲器为主要构建单元的高质量时钟网络管理方法。该时钟网络管理方法通过对高速ADC输出随路时钟的主动干预，解决了多路高速数据锁存困难的问题。实验结果显示：该高速数据采集与处理系统已实现高达1.2 GSPS的采样率以及与之匹配的数据处理速率，有效位数大于8 bit，在实现高速数据采集的同时满足较高分辨力的要求。

Design of high speed data acquisition and processing system based on clock network

A high speed data acquisition and processing system based on clock network is developed aiming at the requirement of high speed data acquisition system in full waveform laser radars. The key techniques are studied in detail. Based on analyzing ChipSync technology and clock jitter, a high quality clock network management method based on PLL and clock buffer is proposed. By using the proposed method which is based on the active intervention of high speed ADC output on-line clock, the problem of multi-channel high speed data flip-latch is solved. Experiment results demonstrate that the realized system can reach the sampling rate of 1.2 GSPS and the Effective Number Of Bit(ENOB) above 8 bit.