An experimental study of scalability in shield-based on-wafer CMOS test fixtures

In this paper, the possibilities of employing full scalability to on-wafer complementary metal-oxide-semiconductor (CMOS) test fixtures is studied experimentally. Several test fixtures and in-fixture sets were fabricated and measured in order to find the significant parasitic components in shield-based fixtures. An improved method for applying bi-directional scaling to on-wafer shield-based test fixtures is proposed. This method takes into account the parasitic series resistance, series inductance, and parallel capacitance that are present in the test fixture. The proposed method can be used successfully in commonly known deembedding methods. This is verified through measurements. The test fixtures were fabricated on top of a lossy substrate using double-poly, three-metal-layer 0.35-/spl mu/m CMOS technology.