| TD-SCDMA中基于块判决反馈的联合检测算法及其VLSI实现 |
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| 引用本文： | 胡东伟,陈杰.TD-SCDMA中基于块判决反馈的联合检测算法及其VLSI实现[J].电子与信息学报,2008,30(5):1180-1184. |
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| 作者姓名： | 胡东伟 陈杰 |
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| 作者单位： | 中国科学院微电子研究所通信与多媒体SoC研究室,北京,100029 |
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| 摘 要： | 为了降低TD-SCDMA的终端成本,该文提出了一种基于块判决反馈的联合检测算法。与已有的联合检测算法相比,该算法以微小的性能损失为代价,极大地降低了计算复杂度,从而使得TD-SCDMA的联合检测协处理器面积小、功耗低、实现容易。在该算法的基础上,该文给出了终端联合检测协处理器的VLSI架构。在0.18m的工艺下该协处理器只有16万门。
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| 关 键 词： | TD-SCDMA 联合检测 VLSI架构 |
| 文章编号： | 1009-5896(2008)05-1180-05 |
| 收稿时间： | 2006-9-11 |
| 修稿时间： | 2006年9月11日 |
Block Decision Feedback based Joint Detection Algorithm for TD-SCDMA and Its VLSI Implementation |
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| Hu Dong-wei,Chen Jie.Block Decision Feedback based Joint Detection Algorithm for TD-SCDMA and Its VLSI Implementation[J].Journal of Electronics & Information Technology,2008,30(5):1180-1184. |
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| Authors: | Hu Dong-wei Chen Jie |
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| Affiliation: | Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China |
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| Abstract: | A new Joint Detection (JD) algorithm, named as Block-Decision-Feedback based Joint Detection (BDF-JD), is proposed for TD-SCDMA. Comparing to the existing algorithms, BDF-JD has much less computational complexity and comparable performance, and is very suitable for terminals. Based on BDF-JD, the architecture of the JD coprocessor is proposed. Implemented with the 0.18 μ m process of SMIC, the coprocessor only consumes 160 k gates. |
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| Keywords: | TD-SCDMA Joint Detection (JD) VLSI architecture |
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