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ArF浸没式光刻在55nm逻辑器件制造中的优势
作者姓名:Takayuki  Uchiyama  Takao  Tamura  Kazuyuki  Yoshimochi  Paul  Graupner  Hans  Bakker  Eelco  van  Setten  Kenji  Morisaki
作者单位:[1]NEC Electronics Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa, Japan, 229-1198 [2]Carl Zeiss, Semiconductor Manufacturing Technology AG, 73447 Oberkochen, Germany [3]ASML, De Run 6501, DR Veldhoven, The Netherlands [4]ASML Japan, 2-15-1 Konan, Minato-ku, Tokyo 108-6022, Japan
摘    要:通过比较干法和浸没光刻技术在超越焦深(DOF)提高方面的一些主要特点,举例说明了采用浸没式光刻技术的许多优势。浸没式光刻技术同干法光刻技术比较起来改善了关键尺寸一致性(CDU)又避开了必需而强硬的分辨率提高技术(RET)。因此利用浸没式光刻技术能够有效地减少光学邻近校正(OPC)的麻烦。就成像技术而言,我们研究了光刻技术对畸变的敏感性和浸没式光刻技术光源光谱带宽对强光相对曝光量对数E95波动性能的优势。去年已经见证了被认为对浸没光刻技术在批量生产中主要难题的套刻精度、缺陷控制和焦平面精度方面有效的改进。如今55nm逻辑器件的生产制造技术要求的挑战已经得到了满足。浸没光刻技术的成就包括抗蚀剂圆片内10nm套刻精度和圆片间20nm的套刻精度,每一圆片上低于10个缺陷以及在整个圆片上40nm以内的焦平面误差。我们形成了一个顶涂层抗蚀剂工艺。总之,浸没光刻技术是55nm节点逻辑器件最有希望的制造生产技术,它可提供与干法ArF光刻技术在CDU控制、套刻性能和焦平面精度方面等效的解决方案,缺陷程度没有增加。NEC电子公司今年采用浸没光刻技术完成了55nm逻辑器件"UX7LS"的开发和试生产并形成这种UX7LS的批量生产光刻技术。

关 键 词:浸没式光刻  55纳米逻辑器件  成像  套刻  关键尺寸一致性
文章编号:1004-4507(2007)11-0008-08
修稿时间:2007-11-05

Benefit of ArF Immersion Lithography in 55 nm Logic Device Manufacturing
Takayuki Uchiyama Takao Tamura Kazuyuki Yoshimochi Paul Graupner Hans Bakker Eelco van Setten Kenji Morisaki.Benefit of ArF Immersion Lithography in 55 nm Logic Device Manufacturing[J].Equipment for Electronic Products Marufacturing,2007,36(11):8-15.
Authors:Takayuki Uchiyama  Takao Tamura  Kazuyuki Yoshimochi  Paul Graupner  Hans Bakker  Eelco van Setten  Kenji Morisaki
Affiliation:1. NEC Electronics Corporation, 1120 Shimokuzawa, Sagamihara, Kanagawa, Japan, 229-1198
2. Carl Zeiss, Semiconductor Manufacturing Technology AG, 73447 Oberkochen, Germany
3. ASML, De Run 6501, DR Veldhoven, The Netherlands
4. ASML Japan, 2-15-1 Konan, Minato-ku, Tokyo 108-6022, Japan
Abstract:In this paper we demonstrate the many benefits of using immersion lithography that go beyond depth of focus (DOF) improvement by comparing several key features of dry and immersion lithography. Immersion lithography improves critical dimension uniformity (CDU) as well as avoiding the necessity for strong resolution enhancement techniques (RET) as compared with dry lithography.Thus it is possible to significantly reduce the burden of optical proximity correction (OPC) work with immersion lithography. With respect to imaging, we studied the sensitivity of the lithographic performances to aberrations and light source spectral bandwidth E95 fluctuations to highlight the benefits of immersion lithography. The significant improvements that have been seen in the last year in overlay accuracy, defect control and focus & leveling accuracy have been considered to be challenges to the realization of immersion lithography in mass production. Now these challenges have been met for the manufacturing requirements of 55 nm logic devices. The achievements of immersion lithography include overlay accuracy within 10 nm on resist-to-resist wafers and within 20 nm on production wafers, fewer than 10 defects per wafer, and errors of less than 40 nm in focus & leveling on full wafers. We have established a top-coat resist process. In conclusion, immersion lithography is the most promising manufacturing solution for 55 nm node logic devices, providing advantages in CDU control,and equivalent overlay performance and focus & leveling accuracy to dry ArF, without an increased level of defects. NEC Electronics has completed development and preproduction of the 55 nm logic device "UX7LS" using immersion lithography and has established the lithography technology for mass production of the UX7LS this year.
Keywords:Immersion lithography  55nm logic device  Imaging  Overlay  CD uniformity
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