基于FPGA的IRIG-B码调制解调实现

旨在设计一种基于FPGA的IRIG-B码的时间系统。该系统采用FPGA作为主控器,利用精准时间信息触发IRIG-B模块,完成IRIG-B码(DC码)的调制。在DC码的基础上,使用容错设计,解调出时间信息。使用VHDL语言进行全数字设计,所有功能都由硬逻辑实现,保证了B码信号沿的准确。软件仿真和示波器以及实际运行表明:系统设计达到了预期目标,定时精确可靠。

Implementation of IRIG-B Modulation and Demodulation Based on FPGA

An IRIG-B code time system based on FPGA is designed in this paper. FPGA is selected as the master controller, B-format code module is triggered by precious time information, and DC code modulation is finished. Time information is demodulated by revising error design on the basic of DC code. Whole digit design is used by VHDL, all function modules provide by hard logic, so that the rising edge of B-format code is accurate and each rising edge can be used as reference point. The design has been verified and tested through simulation and oscilloscope, the practical application proves that the expected goals are achieved perfectly and the timing is precious and dependable.