Fully Pipelined Soft Vector Processor as a CPU Accelerator |
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Affiliation: | Department of Automatic Test and Control, Harbin Institute of Technology, Harbin 150080, China |
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Abstract: | FPGA based soft vector processing accelerators are used frequently to perform highly parallel data processing tasks. Since they are not able to implement complex control manipulations using software, most FPGA systems now incorporate either a soft processor or hard processor. A FPGA based AXI bus compatible vector accelerator architecture is proposed which utilises fully pipelined and heterogeneous ALU for performance, and microcoding is employed for reusability. The design is tested with several design examples in four different lane configurations. Compared with Central processing unit (CPU), Digital signal processor (DSP), Altera C2H tool and OpenCL SDK implementations, the vector processor improves on execution time and energy consumption by factors of up to 6.6 and 6.4 respectively. |
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Keywords: | FPGA Vector processor Microprocessor Accelerator |
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