A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment |
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Authors: | Hong-Sik Kim Sungho Kang Michael S Hsiao |
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Affiliation: | (1) Department of Electrical and Electronic Engineering, Yonsei University, Shinchondong, Seodaemungu, Seoul, Korea;(2) Bradley Department of Electrical and Computer Engineering, Virginia Tech., Blacksburg, VA, USA |
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Abstract: | A new scan architecture for both low power testing and test volume compression is proposed. For low power test requirements,
only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells
according to the distribution of unspecified bits in the test cubes. In order to optimize the proposed process, a novel graph-based
heuristic is proposed to partition the scan chains into several segments. For test volume reduction, a new LFSR reseeding
based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, s
max, virtually. The performance of a conventional LFSR reseeding scheme highly depends on s
max. In this paper, by using different clock phases between an LFSR and scan chains, and grouping the scan cells by a graph-based
grouping heuristic, s
max could be virtually reduced. In addition, the reduced scan rippling in the proposed test compression scheme can contribute
to reduce the test power consumption, while the reuse of some test results as the subsequent test stimulus in the low power
testing scheme can reduce the test volume size. Experimental results on the largest ISCAS89 benchmark circuits show that the
proposed technique can significantly reduce both the average switching activity and the peak switching activity, and can aggressively
reduce the volume of the test data, with little area overhead, compared to the previous methods.
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Keywords: | Keyword" target="_blank">Keyword System on a chip Scan testing Low power testing Test compression |
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