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Optimum architecture for input queuing ATM switches |
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| Authors: | Majumder SP Gangopadhyay R |
| Affiliation: | Dept. of Electron. & Electr. Commun. Eng., Indian Inst. of Technol., Kharagpur, India; |
| Abstract: | An input queueing ATM switch architecture employing the contention resolution called 'scheduling algorithm' is described. A high efficiency of over 90% can be achieved without any considerable increase in the amount of hardware or contention control speed.< |
| Keywords: | |