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DFE architectures for high-speed backplane applications |
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| Authors: | Li M Wang S Kwasniewski T |
| Affiliation: | Dept. of Electron., Carleton Univ., Ottawa, Ont., Canada; |
| Abstract: | Embedded and look-ahead decision feedback equalisation (DFE) architectures are proposed to overcome the speed bottleneck of DFE design for high-speed backplane applications. DFE design examples simulated in 0.18 /spl mu/m CMOS technology demonstrate the feasibility of 10Gbit/s operation over a 34-inch FR4 backplane. |
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