| H.264中自适应二进制算术编码的IP核设计及其FPGA验证 |
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| 引用本文： | 付遥,周东辉. H.264中自适应二进制算术编码的IP核设计及其FPGA验证[J]. 微计算机信息, 2006, 22(2): 163-165 |
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| 作者姓名： | 付遥 周东辉 |
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| 作者单位： | 266001,青岛中国海洋大学信息学院 |
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| 摘 要： | 阐述H.264/AVC二进制算术编码的原理,论述此编码的IP核设计方案及其FPGA验证。整个设计使用VerilogHDL语言描述,在ALDEC的Active_HDL6.2平台上进行时序仿真,在Synplicity的Synplify7.0平台上进行综合。设计充分利用了硬件并行性,并进行关键路径优化和复用器重构算法优化,通过实际验证证明了设计的高效性和可行性。
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| 关 键 词： | 二进制算术编码 |
| 文章编号： | 1008-0570(2006)01-2-0163-03 |
| 修稿时间： | 2005-06-26 |
IP core design for adaptive binary arithmetic coding in the H.264/AVC and its FPGA verification |
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| Fu,Yao,Zhou,Donghui. IP core design for adaptive binary arithmetic coding in the H.264/AVC and its FPGA verification[J]. Control & Automation, 2006, 22(2): 163-165 |
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| Authors: | Fu Yao Zhou Donghui |
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| Abstract: | This paper introduces the principle of the adaptive binary arithmetic coding in the H.264/AVC . It gives the IP core solution for this coding and its FPGA verification . The design discribed by VerilogHDL , and emluated sucessfully on Active_HDL6.2. It is synthesized on Synplify7.0. The design is optimized by the method of perfecting critical path and Multiplexer restructuring. It is proved that the design is high-powered and viable by experiments. |
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| Keywords: | IP VerilogHDL FPGA |
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