A latch-up-like new failure mechanism for high-density CMOS dynamicRAMs

A latch-up-like failure phenomenon that shows hysteresis in the V_cc-I_cc characteristics observed in a high-density CMOS dynamic RAM that utilizes an on-chip substrate-bias generator is discussed. This failure is caused by large substrate-current generation due to the depletion-mode threshold voltage of n-channel transistors at near-zero substrate-bias operation. It is increasingly important not only to design a powerful substrate-bias generator but also to suppress the back-gate bias effect on the n-channel transistor