An optimal scheduling algorithm for testing interconnect using boundary scan

Systems will soon be built with ICs that conform with the IEEE 1149.1 boundary scan architecture. Due to the hierarchical nature of such systems, they may contain many boundary scan chains. These chains can be used to test the system, subsystem, and board interconnect. To reduce test time, the application of test vectors to these scan chains must be carefully scheduled. This article deals with problems related to finding an optimal schedule for testing interconnect. This problem is modeled using a directed graph. The following results are obtained: (1) upper and lower bounds on interconnect test time; (2) necessary and sufficient conditions for obtaining an optimal schedule when the graph is acyclic; (3) sufficient condition for obtaining an optimal schedule when the graph is cyclic; and (4) an algorithm for constructing an optimal schedule for any graph.This work was supported by Defense Advanced Research Projects Agency and monitored by the Office of Naval Research under contract No. N00014-87-K-0861. The views and conclusions contained in this document are those of the authors and should not be interpreted as necessarily representing the official policies, either expressed or implied, of the Defense Advanced Research Projects Agency or the U.S. Government.