Trimming process and temperature variation in second-order bandgap voltage reference circuits |
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Authors: | Rajarshi Paul Amit Patra |
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Affiliation: | Department of Electrical Engineering, Indian Institute of Technology, Kharagpur, India |
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Abstract: | This paper presents the design and experimental performance of a second-order bandgap voltage reference integrated circuit (IC). Experimentally observed nominal reference voltage at room temperature is 1.150 V with best temperature performance of 3 mV variation over −40 to 120 °C. A 5-bit resistor trimming is used to compensate the variation of reference voltage due to layout mismatch and process variation. A trimming methodology is described in this paper to optimize both the temperature performance and reduce the variation of the room temperature voltage over different samples. Even with best temperature performance trim-code, the absolute variation in reference voltage over 20 samples is 85 mV which is trimmed to ±11 mV (1.3%) using the proposed trimming methodology. The second-order bandgap circuit is designed in a 0.5 μm BiCMOS process with less than 50 μA current consumption. |
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Keywords: | Bandgap voltage reference PTAT CTAT Temperature and process compensation Post-fabrication trimming design BiCMOS process |
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