Enhanced source-degenerated CMOS differential transconductor |
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Authors: | J.M. Martinez-Heredia A. Torralba |
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Affiliation: | Department of Electronic Engineering, School of Engineering, Camino de los Descubrimientos, s/n. 41092 Seville, Spain |
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Abstract: | A simple technique to improve the output resistance and the linearity of a source-degenerated differential CMOS transconductor is presented, useful even under low supply voltage. It combines the utilization of a super-transistor as a unity-gain buffer and the use of the weak inversion region to optimize a regulated cascode source. Using a standard 0.13 μm CMOS technology with 1.5 V supply voltage, simulation results show the transconductor attains more than 1 GΩ as differential output resistance and a third-order harmonic distortion factor less than −110 dB at 1 kHz for a 0.35 Vpp differential input signal. Other performances are 126 μW power consumption and 65 MHz bandwidth. |
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Keywords: | CMOS Linear transconductor High output resistance Low-voltage design |
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