Low-voltage, high-speed CMOS analog latched voltage comparator using the “flipped voltage follower” as input stage |
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Authors: | Hugues J Achigui Christian Fayomi Daniel Massicotte |
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Affiliation: | a Department of Computer Science, Université du Québec à Montréal, Montréal, Canada b Department of Electrical and Computer Engineering, Université du Québec à Trois-Rivières, Trois-Rivières, Canada |
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Abstract: | The design and characterization of a low-voltage, high-speed CMOS analog latched voltage comparator based on the flipped voltage follower (FVF) cell and input signal regeneration is presented. The proposed circuit consists of a differential input stage with a common-mode signal detector, followed by a regenerative latch and a Set-Reset (S-R) latch. It is suitable for successive-approximation type’s analog-to-digital converters (ADC), but can also be adapted for use in flash-type ADCs. The circuit was fabricated using 0.18 μm CMOS technology, and its measured performance shows 12-bit resolution at 20 MHz comparison rate and 1 V single supply voltage, with a total power consumption of 63.5 μW. |
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Keywords: | Flipped voltage follower Low-voltage Analog CMOS voltage comparator Kickback noise |
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