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New Mix codes for multiple bit upsets mitigation in fault-secure memories
Authors:Ming Zhu  Li Li Song  Hong Wei Luo
Affiliation:a Microelectronics Center, Harbin Institute of Technology, 150001 Harbin, China
b National Key Laboratory of Science and Technology on Reliability Physics and Application Technology of Electrical Component, 510610 Guangzhou, China
Abstract:Nowadays, multibit error correction codes (MECCs) are effective approaches to mitigate multiple bit upsets (MBUs) in memories. As technology scales, combinational circuits have become more susceptible to radiation induced single event transient (SET). Therefore, transient faults in encoding and decoding circuits are more frequent than before. Firstly, this paper proposes a new MECC, which is called Mix code, to mitigate MBUs in fault-secure memories. Considering the structure characteristic of MECC, Euclidean Geometry Low Density Parity Check (EG-LDPC) codes and Hamming codes are combined in the proposed Mix codes to protect memories against MBUs with low redundancy overheads. Then, the fault-secure scheme is presented, which can tolerate transient faults in both the storage cell and the encoding and decoding circuits. The proposed fault-secure scheme has remarkably lower redundancy overheads than the existing fault-secure schemes. Furthermore, the proposed scheme is suitable for ordinary accessed data width (e.g., 2n bits) between system bus and memory. Finally, the proposed scheme has been implemented in Verilog and validated through a wide set of simulations. The experiment results reveal that the proposed scheme can effectively mitigate multiple errors in whole memory systems. They can not only reduce the redundancy overheads of the storage array but also improve the performance of MECC circuits in fault-secure memory systems.
Keywords:Multiple bit upsets  Multibit error correction codes  Fault-secure memory  ECC  EG-LDPC codes  Single event transient
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