Ultra low power phase detector and phase-locked loop designs and their application as a receiver |
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Authors: | Bo Li Bo Yang Martin Peckerar |
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Affiliation: | a Department of Electrical and Computer Engineering, University of Maryland, College Park, MD 20742, USA b Laboratory for Physical Sciences, College Park, MD 20740, USA |
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Abstract: | In this paper, we present a new low power down-conversion mixer design with single RF and LO input topology which consumes 48 μW power. Detailed analysis of the mixer has been provided. Using the presented mixer as a phase-detector, a low power phase-locked loop (PLL) has been designed and fabricated. A PLL based receiver architecture has been developed and analyzed. The circuit has been fabricated through 0.13 μm CMOS technology. Dissipating 0.26 mW from a 1.2 V supply, the fabricated PLL can track signals between 1.62 and 2.49 GHz. For receiver applications, the energy per bit of the receiver is only 0.26 nJ making it attractive for low power applications including wireless sensor networks. |
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Keywords: | Low power mixer Phase detector Ring oscillator VCO Phase-locked loops (PLL) Frequency-modulation (FM) receiver Frequency-shift keying (FSK) |
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