| SEU/SET加固D触发器的设计与分析 |
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| 引用本文： | 黄晔,程秀兰.SEU/SET加固D触发器的设计与分析[J].半导体技术,2009,34(1). |
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| 作者姓名： | 黄晔 程秀兰 |
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| 作者单位： | 上海交通大学微电子学院,上海,200240 |
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| 摘 要： | 针对D触发器的抗单粒子辐射效应加固,提出了一种新型的保护门触发器(GGFF)设计,使用两个保护门锁存器串接成主从触发器.通过Spice仿真验证了GGFF抗SEU/SET的能力,通过比较和分析,证明GGFF对于具有同样抗SEU/SET能力的时间采样触发器(TSFF),在电路面积和速度上占据明显优势.
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| 关 键 词： | 单粒子效应 D触发器 保护门 |
Design and Analysis of SEU/SET Hardened D Flip-Flop |
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| Huang Ye,Cheng Xiulan.Design and Analysis of SEU/SET Hardened D Flip-Flop[J].Semiconductor Technology,2009,34(1). |
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| Authors: | Huang Ye Cheng Xiulan |
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| Affiliation: | School of Microelectronics;Shanghai Jiao Tong University;Shanghai 200240;China |
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| Abstract: | A novel guard gate flip-flop(GGFF) design was proposed for mitigating D flip-flop single event effects.Master-slave flip-flop was constructed by two guard gate latches connected in series.Spice simulation was utilized to verify that GGFF can mitigate SEU and SET.After comparison and analysis it can be proved that GGFF is much better in chip size and speed than temporal sampling flip-flop(TSFF),which can also mitigate SEU and SET. |
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| Keywords: | single event effects D flip-flop guard gate |
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