| 异步可重构结构设计 |
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| 引用本文： | 季爱明,沈海斌,严晓浪. 异步可重构结构设计[J]. 电路与系统学报, 2007, 12(2): 56-60 |
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| 作者姓名： | 季爱明 沈海斌 严晓浪 |
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| 作者单位： | 浙江大学,超大规模集成电路设计研究所,浙江,杭州310027 |
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| 基金项目： | 国家863计划资助课题（2003AA14059,2003AA1Z1060） |
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| 摘 要： | 介绍一种异步可重构结构，研究了异步可重构单元的设计。通过提前产生求值完成信号，使用DSDCVS逻辑实现可重构单元的运算电路，改进了异步可重构单元的控制电路。用三输入的C元件实现异步可重构单元的控制电路。仿真结果表明，异步可重构结构具有低功耗、高性能的优点，适合作为IP集成到系统芯片上，组成低功耗、高性能的可重构计算平台。
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| 关 键 词： | 异步可重构结构 求值完成信号 控制电路 运算电路 |
| 文章编号： | 1007-0249（2007）02-0056-05 |
| 收稿时间： | 2005-05-24 |
| 修稿时间： | 2005-07-14 |
The design of asynchronous reconfigurable architecture |
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| JI Ai-ming,SHEN Hai-bin,YAN Xiao-lang. The design of asynchronous reconfigurable architecture[J]. Journal of Circuits and Systems, 2007, 12(2): 56-60 |
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| Authors: | JI Ai-ming SHEN Hai-bin YAN Xiao-lang |
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| Abstract: | A novel asynchronous reconfigurable architecture is introduced in this paper. The design of asynchronous reconfigurable cell is studied. By producing evaluating completion signal early and using DSDCVS logic to design computation circuit of reconfigurable cell, a modified control circuit is proposed. C element is used to design the control circuit for asynchronous reconfigurable cell. Simulation results show that asynchronous reconfigurable architecture has advantage of low power and high performance, and it can be used as a IP module which is integrated into system on chip to build a reconfigurable computing platform. |
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| Keywords: | asynchronous reconfigurable architecture evaluating completion signal control circuit computation circuit |
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