| PL4接口在FPGA中的设计与实现 |
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| 引用本文： | 张树旗,杜海兵. PL4接口在FPGA中的设计与实现[J]. 微计算机信息, 2005, 0(13) |
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| 作者姓名： | 张树旗 杜海兵 |
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| 作者单位： | 郑州信息工程大学国家数字交换系统工程技术研究中心 450002(张树旗)，郑州信息工程大学国家数字交换系统工程技术研究中心 450002(杜海兵) |
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| 摘 要： | 介绍了利用Altera公司的StratixGX系列FPGA器件实现POS-PHYLevel4接口协议的工作原理、设计思想和电路结构,并详细讨论了一种计算128位数据的4位对角交叉奇偶校验码DIP-4的适合硬件实现的算法,该算法在实际应用中功能正确且实现简单方便。
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| 关 键 词： | POS-PHYLevel4(PL4) 现场可编程门阵列(FPGA) 对角交叉奇偶校验(DIP) |
Design and Realization of the Interface Protocol of the POS- PHY Level 4 Based on FPGA |
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| Zhang,Shuqi Du,Haibing. Design and Realization of the Interface Protocol of the POS- PHY Level 4 Based on FPGA[J]. Control & Automation, 2005, 0(13) |
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| Authors: | Zhang Shuqi Du Haibing |
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| Abstract: | This article introduced a method to realize the inter-face protocol of POS- PHY Level 4 based on FPGA, and giventhe operation principle and the block diagram of the design.Further more, a method to calculate the 4 bits diagonal inter-leaved parity code (DIP- 4) for the data of 128- bits was shown,and in our practical application, it is easy to realize and worksvery well. |
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| Keywords: | POS- PHY Level 4 (PL4) Field ProgrammableGate Array (FPGA) diagonal interleaved parity (DIP) |
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