柔性结构的AES加密芯片设计

提出了基于有限域运算单元的柔性AES加密系统。通过对不同密钥扩展的算法进行比较分析,利用其基本运算单元相同的特性,采用控制单元实现可支持128位、192位和256位三种密钥长度的柔性结构。采用集成化的可重构柔性AES加密系统,可以降低硬件逻辑资源消耗。使用Verilog HDL硬件语言进行仿真,并在0.35μm工艺下进行逻辑综合。结果表明,时钟频率可达180 MHz,对于128位密钥长度,系统吞吐量可达2.11 Gbps。

Design of AES Enciphered IC with Flexible Structure

An AES enciphered algorithm was proposed based on finite field operation unit. Different key expansions were compared and analyzed. A flexible structure for key lengths of 128-bit, 192-bit and 256-bit was implemented by multiplexing the same module and control module. By using the integrated reconfigurable AES system, hardware logic units could be reduced. The circuit was simulated using Verilog HDL and synthesized based on 0.35-μm CMOS technology. Results showed that the system achieved a data throughput of 2.11 Gbps with a clock frequency of 180 MHz in AES-128 mode.