基于FPGA的数字射频存储器设计

数字射频存储器(DRFM)是电子对抗中的一个关键部件,它将雷达信号下变频后的信号进行采样保存,再延时转发出去,从而实现距离上的欺骗干扰.本文介绍了DRFM的基本原理,确定了目前的总体设计思想,并在此基础上,设计了一种基于现场可编程门阵列的方案,并对方案进行了详细的论证.另外,对方案的核心部分还进行了仿真,分析了系统的主要性能指标.这种方案的设计思想独到,采用器件先进,为进一步研制高性能的DRFM电路奠定了坚实的基础.

Design of DRFM based on FPGA

Digital RF memory is a key component of the electronic jammer.It samples and saves the signal which is from down frequency conversion of radar signal,then postpones and sends it out,thus the deception and interference in distance are realized.This paper introduces the basic working principle of DRFM,and makes sure the current design thought.On this foundation,this paper designs a kind of DRFM basis of FPGA and demonstrates it.Moreover,the simulation of the core component has done and analyses the target of system's performance.The design thought of this project is original,the parts of an apparatus is forerunner,to further research the electric circuit of DRFM lay the solid foundation.