| 数字信号处理模块中的串行RapidIO设计 |
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| 引用本文： | 张静.数字信号处理模块中的串行RapidIO设计[J].火控雷达技术,2011,40(1):64-67,75. |
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| 作者姓名： | 张静 |
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| 作者单位： | 西安电子工程研究所,西安,710100 |
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| 摘 要： | RapidIO互连构架是一种基于可靠性的开放式标准,可应用于连接多处理器、存储器和通用计算机平台.本文基于集成双核处理器MPC8641D和FPGA芯片XC5VSX240T的数字信号处理平台,进行了串行RapidIO(SRIO)技术的开发.文中给出了SRIO互连架构的硬件设计方案以及MPC8641D中SRIO数据通信软件...
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| 关 键 词： | SRIO CPU FPGA |
Design of Serial RapidIO in Digital Signal Processing Module |
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| Zhang Jing.Design of Serial RapidIO in Digital Signal Processing Module[J].Fire Control Radar Technology,2011,40(1):64-67,75. |
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| Authors: | Zhang Jing |
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| Affiliation: | Zhang Jing(Xi′an Electronic Engineering Research Institute,Xi′an 710100) |
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| Abstract: | RapidIO interconnection framework is an open standard based on reliability,which can be applied to connect multi-processor,memory and common computer platform.Based on the digital signal processing platform with dual-core processor MPC8641D and FPGA chip XC5VSX240T,serial RapidIO(SRIO) technology is developed.Hardware design approach of SRIO interconnect framework and design flow of SRIO data communication software in MPC8641D is provided,and high data rate(10Gbit/s) interconnection between CPU and FPGA is achieved. |
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| Keywords: | SRIO CPU FPGA |
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