An FPGA-based low-cost VLIW floating-point processor for CNC applications |
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| Affiliation: | 1. School of Mechanical Engineering, Tianjin University, Tianjin 300354, PR China;2. Key Laboratory of Mechanism Theory and Equipment Design of Ministry of Education, Tianjin University, Tianjin 300354, PR China;1. Chair of Technical Electronics, Technical University of Munich (TUM), Germany;2. Chair of Electronic Design Automation, Technical University of Munich (TUM), Germany;1. Department of Computer Science and Information Engineering, National Taitung University, Taiwan;2. School of Computing Informatics and Decision Systems Engineering, Arizona State University, USA;3. Department of Computer Science and Information Engineering, National Chung Cheng University, Taiwan;1. The George Washington University, Department of Electrical and Computer Engineering, Science & Engineering Hall, 800 22nd St NW, Washington, D.C., 20052;2. New Mexico State University, Klipsch School of Electrical and Computer Engineering, Thomas & Brown Hall, 1125 Frenger Mall, Las Cruces, NM 88003;1. Advanced Analog Systems Chair, CentraleSupélec, 3 Rue Joliot Curie, F-91192 Gif-Sur-Yvette Cedex, France;2. Group of Electrical Engineering Paris, UMR CNRS 8507, CentraleSupélec, Univ. Paris-Sud, Univ. Paris-Saclay, Sorbonne Univ., UPMC Univ Paris 06, F-91192 Gif-Sur-Yvette Cedex, France;3. 31 Boulevard Dolez, 7000 Mons, Belgium;1. Variable Energy Cyclotron Center, HBNI,1/AF Bidhannagar, Kolkata 700064, India;2. A.K.Choudhury School of Information Technology, University of Calcutta, Sector-3, Salt lake City, Kolkata 700098, India |
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| Abstract: | In the high-speed free-form surface machining, the real-time motion planning and interpolation is a challenging task. This paper presents the design and implementation of a dedicated processor for the interpolation task in computerized numerical control (CNC) machine tools. The jerk-limited look-ahead motion planning and interpolation algorithm has been integrated in the interpolation processor to achieve smooth motion in the high-speed machining. The processor features a compactly designed floating-point parallel computing architecture, which employs a 3-stage pipelined reduced instruction set computer (RISC) core and a very long instruction word (VLIW) floating-point arithmetic unit. A new asynchronous execution mechanism has been employed in the processor to allow multi-cycle instructions to be performed in parallel. The proposed processor has been verified on a low-cost field programmable gate array (FPGA) chip in a prototype controller. Experimental result has demonstrated the significant improvement of the computing performance with the interpolation processor in the free-form surface machining. |
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