Optimizing power efficiency for 3D stacked GPU-in-memory architecture |
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| Affiliation: | 1. Department of Electrical and Computer Engineering, University of Pittsburgh, Pittsburgh, USA;2. Department of Computer Science, University of Pittsburgh, Pittsburgh, USA;1. Chair of Technical Electronics, Technical University of Munich (TUM), Germany;2. Chair of Electronic Design Automation, Technical University of Munich (TUM), Germany;1. The George Washington University, Department of Electrical and Computer Engineering, Science & Engineering Hall, 800 22nd St NW, Washington, D.C., 20052;2. New Mexico State University, Klipsch School of Electrical and Computer Engineering, Thomas & Brown Hall, 1125 Frenger Mall, Las Cruces, NM 88003;1. School of Electronic Engineering, Sudan University of Science and Technology, Khartoum, Sudan;2. School of Electrical and Electronic Engineering, Universiti Sains Malaysia, Nibong Tebal 14300, Penang, Malaysia;1. Advanced Analog Systems Chair, CentraleSupélec, 3 Rue Joliot Curie, F-91192 Gif-Sur-Yvette Cedex, France;2. Group of Electrical Engineering Paris, UMR CNRS 8507, CentraleSupélec, Univ. Paris-Sud, Univ. Paris-Saclay, Sorbonne Univ., UPMC Univ Paris 06, F-91192 Gif-Sur-Yvette Cedex, France;3. 31 Boulevard Dolez, 7000 Mons, Belgium;1. Seoul National University, Republic of Korea\n;2. Chonbuk National University, Republic of Korea\n;1. Madeira Interactive Technologies Institute, Funchal, Portugal;2. University of Madeira, Funchal, Portugal;3. University of Las Palmas de Gran Canaria, Las Palmas de Gran Canaria, Spain |
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| Abstract: | With the prevalence of data-centric computing, the key to achieving energy efficiency is to reduce the latency and energy cost of data movement. Near data processing (NDP) is a such technique which, instead of moving data around, moves computing closer to where data is stored. The emerging 3D stacked memory brings such opportunities for achieving both high power-efficiency as well as less data movement overheads. In this paper, we exploit power efficient NDP architectures using the 3D stacked memory. We integrate the programmable GPU streaming multiprocessors into the NDP architectures, in order to fully exploit the bandwidth provided by 3D stacked memory. In addition, we study the tradeoffs between area, performance and power of the NDP components, especially the NoC designs. Our experimental results show that, compared to traditional architectures, the proposed GPU based NDP architectures can achieve up to 43.8% reduction in EDP and 41.9% improvement in power efficiency in terms of performance-per-Watt. |
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