Decimal addition on FPGA based on a mixed BCD/excess-6 representation |
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| Affiliation: | 1. INESC-ID, Instituto Superior Técnico, Universidade de Lisboa, Portugal;2. INESC-ID, ISEL, Instituto Politécnico de Lisboa, Portugal;1. Oncology Department of Peking Union Medical College Hospital, Chinese Academy of Medical Sciences, No. 1 ShuaiFuYuan Hutong, Dongcheng District, Beijing 100730, People''s Republic of China;2. Peking Union Medical College, Chinese Academy of Medical Sciences, No. 5 DongDanSanTiao, Dongcheng District, Beijing 100005, People''s Republic of China;3. Laboratory of Cell and Molecular Biology & State Key Laboratory of Molecular Oncology, Cancer Institute & Cancer Hospital, Chinese Academy of Medical Sciences & Peking Union Medical College, No. 17 Panjiayuan Nanli, Chaoyang District, Beijing 100021, People''s Republic of China |
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| Abstract: | Decimal arithmetic has recovered the attention in the field of computer arithmetic due to decimal precision requirements of application domains like financial, commercial and internet. In this paper, we propose a new decimal adder on FPGA based on a mixed BCD/excess-6 representation that improves the state-of-the-art decimal adders targeting high-end FPGAs. Using the proposed decimal adder, a multioperand adder and a mixed binary/decimal adder are also proposed. The results show that the new decimal adder is very efficient improving the area and delay of previous state of the art decimal adders, multioperand decimal addition and binary/decimal addition. |
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