A 0.3-μm CMOS 8-Gb/s 4-PAM serial link transceiver |
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Authors: | Farjad-Rad R. Yang C.-K.K. Horowitz M.A. |
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Affiliation: | Center for Integrated Syst., Stanford Univ., CA ; |
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Abstract: | An 8-Gb/s 0.3-μm CMOS transceiver uses multilevel signaling (4-PAM) and transmit preshaping in combination with receive equalization to reduce intersymbol interference due to channel low-pass effects. High on-chip frequencies are avoided by multiplexing and demultiplexing the data directly at the pads. Timing recovery takes advantage of a novel frequency acquisition scheme and a linear phase-locked loop that achieves a loop bandwidth of 35 MHz, phase margin of 50°, and capture range of 20 MHz without a frequency acquisition aid. The transmitted 8 Gb/s data are successfully detected by the receiver after a 10-m coaxial cable. The 2×2 mm2 chip consumes 1.1 W at 8 Gb/s with a 3-V supply |
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