一种面向基于闪存的脉冲卷积神经网络的模拟神经元电路

该文面向基于闪存(Flash)的脉冲卷积神经网络(SCNN)提出一种积分发放(IF)型模拟神经元电路，该电路实现了位线电压箝位、电流读出减法和积分发放功能。为解决低电流读出速度较慢的问题，该文设计一种通过增加旁路电流大幅提高电流读出范围和读出速度的方法；针对传统模拟神经元复位方案造成的阵列信息丢失问题，提出一种固定泄放阈值电压的脉冲神经元复位方案，提高了阵列电流信息的完整性和神经网络的精度。基于55 nm 互补金属氧化物半导体(CMOS)工艺对电路进行设计并流片。后仿结果表明，在20 μA电流输出时，读出速度提高了100%，在0 μA电流输出时，读出速度提升了263.6%，神经元电路工作状态良好。测试结果表明，在0～20 μA电流输出范围内，箝位电压误差小于0.2 mV，波动范围小于0.4 mV，电流读出减法线性度可达到99.9%。为了研究所提模拟神经元电路的性能，分别通过LeNet和AlexNet对MNIST和CIFAR-10数据集进行识别准确率测试，结果表明，神经网络识别准确率分别提升了1.4%和38.8%。

An Analog Neuron Circuit for Spiking Convolutional Neural Networks Based on Flash Array

In this paper, an Integrate-and-Fire (IF) analog readout neuron circuit is proposed for Spiking Convolutional Neural Network (SCNN) based on flash array. The circuit realizes the following functions: bit line voltage clamping, current readout, current subtraction, and integrate-and-fire. A current readout method is proposed to improve the current readout range and speed by increasing by-pass current. To avoid the loss of array information caused by the traditional analog neuron reset scheme, a reset scheme with subtracting threshold voltage is proposed, which improves the integrity of information and the accuracy of the neural network. The circuit is implemented in 55 nm Complementary Metal Oxide Semiconductor (CMOS) process. Simulation results show that when output current is 20 μA and 0 μA, the read speed can be accelerated 100% and 263.6% respectively; The neuron circuit works well. And test results show that, in the current output range of 0～20 μA, the clamp voltage error is less than 0.2 mV and the fluctuation is less than 0.4 mV; The linearity of current subtraction can reach 99.9%. To study the performance of the analog neuron circuit, LeNet and AlexNet algorithm with circuit model for the recognition of the MNIST and CIFAR-10 database is tested. Test results illustrate that the neural network accuracy is improved by 1.4% and 38.8%.