Extraction of trap densities in entire bandgap of poly-Si thin-film transistors fabricated by solid-phase crystallization and dependence on process conditions of post annealing

Trap densities (D_t) in entire bandgaps of poly-Si thin-film transistors (TFTs) fabricated by solid-phase crystallization (SPC) have been extracted by measuring low-frequency capacitance-voltage characteristics and using an extraction algorithm. The extraction algorithm is explained in detail. D_t in the upper and lower halves of the bandgap is extracted from n- and p-type TFTs, respectively. It is found that D_t is very roughly 10¹⁸ cm⁻³ eV⁻¹ near the midgap and becomes tail states near the conduction and valence bands. As a result, D_t is distributed like U shape in the bandgap, but humps appear around the midgap. Moreover, the dependence of D_t on process conditions of post annealing has been evaluated. It is found that the hump can be reduced by increasing annealing temperature and time because crystal defects generated during the SPC are extinguished during the post annealing.