应用于片上系统中低功耗IP核设计的自适应门控时钟技术

门控时钟技术一直以来是降低芯片动态功耗的有效方法.文章结合片上系统(SoC)的结构特性和设计特点,分析已有的各种门控时钟技术的优缺点,指出这些缺点是SoC设计中的严重障碍,随后抽象出IP核工作模型,提出了仅用非常简单的逻辑就可以方便应用于IP核的自适应门控时钟技术.这种技术在不影响性能的前提下,可以根据IP核的应用状况自动开关时钟,不但可以降低动态功耗,还可以结合门控电源技术降低漏电功耗.对一款真实SoC中浮点IP核的改造实验表明,在不降低性能的前提下,可以平均降低62.2%的动态功耗,同时理论上平均降低70.9%的漏电功耗.

Adaptive Clock Gating Technique for Low Power IP Core Design in SoC

Clock gating is a well-known technique to reduce dynamic power.This paper analyses the disadvantages of many clock gating techniques and points out that they are obstacles in System-on-Chip(SoC) design.Based on the analysis of IP core model and the programmable clock gating technique,an adaptive clock gating(ACG) technique which can be easily realized is introduced for low power IP core design.ACG can automatically turn on or turn off the IP clock to not only reduce dynamic power but also reduce leakage power with the power gating technique.The experimental results on some IP cores in a real SoC show an average of 62.2% dynamic power reduction and 70.9% leakage power reduction without performance degradation.