Distributed crossbar architecture for area-efficient combined data/instruction caches with multiple ports |
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| Authors: | Johguchi K Zhu Z Hirakawa T Koide T Hironaka T Mattausch HJ |
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| Affiliation: | Res. Center for Nanodevices & Syst., Hiroshima Univ., Higashi-Hiroshima, Japan; |
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| Abstract: | A proposal to improve the low access bandwidth of conventional one-port caches by utilising a multi-bank structure with distributed crossbar to increase port number at small additional area cost is presented. This enables combination of data and instruction caches into a single multi-port cache as well as different wordlength for each port. Through dynamically scheduling the storage space used for data and instructions, 25% smaller storage capacity is sufficient for a given maximum cache-miss probability. |
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