一种基于改进DES算法的高效率FPGA硬件实现

针对DES密钥空间小、抗攻击能力弱的缺点,提出了一种改进S-BOX及相关密钥的DES算法.这种体制增强了穷举法攻击、线性密码分析攻击、差分密码分析攻击的难度,大大降低了信息被窃取的概率.由于硬件实现DES密钥模块内部运作,既可保证在外界无密钥的明文流动,又可具备自锁、自毁功能,具有高速、高可靠性等特点,所以利用VHDL硬件描述语言实现了改进的简化DES算法.实验验证,该方案可以抵抗线性密码分析,确保密码体制没有"陷门",实现真正意义上的保密,同时有效地节约了硬件资源.

A high efficient FPGA implementation based on an improved DES algorithm

After an introduction of DES algorithm and an analysis of related formulas used in the DES,to aim at the disadvantages of small space and weak anti-attack capability,this paper proposed an improvement in the key to the algorithm and the S-Box.This system increased attacking the difficulties of the exhaustive attacks,the linear cryptanalysis attacks and differential cryptanalysis attacks,and reduced the probability of information being stolen.The Internal operations of DES Key Module implemented by the hardw...