| 短波接收机数字锁相频率合成器的设计 |
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| 引用本文： | 周玉锋,吴青萍.短波接收机数字锁相频率合成器的设计[J].常州信息职业技术学院学报,2012,11(5):22-24,83. |
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| 作者姓名： | 周玉锋 吴青萍 |
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| 作者单位： | 1. 常州无线电厂有限公司,江苏常州,213025
2. 常州信息职业技术学院,江苏常州,213164 |
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| 摘 要： | 提出了基于DDS/PLL混合的频率合成器的设计方案,给出了主要的硬件选择,并且对该频率合成器的杂波抑制和相位噪声进行了分析,最后对样机的性能进行了测试,结果表明该频率合成器具有很好的性能,可应用于短波接收机中。
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| 关 键 词： | 数字直接频率合成器 锁相频率合成器 AD9851 相位噪声 |
Design of Digital Phase-locked Frequency Synthesizer Used in Short-wave Receiver |
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| ZHOU Yu-feng,WU Qing-ping.Design of Digital Phase-locked Frequency Synthesizer Used in Short-wave Receiver[J].Journal of Changzhou Vocational College of Information Technology,2012,11(5):22-24,83. |
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| Authors: | ZHOU Yu-feng WU Qing-ping |
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| Affiliation: | 2 ( 1.Changzhou Radio Factory Lhnited Company, Changflaou 213025, China; 2.School of Electronic and Electrical Engineering, ClmngZhou College of kiformation Technology, Changzhou 213164, China) |
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| Abstract: | This paper presents a design scheme of frequency synthesizer based on DDS/PLL, gives the rmm hardware devices, analyzes the phase noise and the resa＇ahlt of noise. At last, the performance of the prototype machine is measured, results show that this frequency synthesizer can perform well; it can be used in shortwavereceiver. |
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| Keywords: | DSS PLL AD9851 phase noise |
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