一种全并行LDPC译码器及FPGA实现方法

低密度校验(Low-Density Parity-Check)码作为迄今为止性能接近香农限的前向纠错码(FEC)之一，在无线通信、卫星通信和无线网络技术等领域获得了广泛的应用。随着 5G 技术的发展，通信系统对传输速率的需求逐渐增加，更高的传输速率对 LDPC 译码器的吞吐量提出了更高的要求。本文给出了一种全并行 LDPC 译码器设计，并采用理论分析和仿真结果分析相结合的方法，对 LDPC 码的并行译码方法进行了研究，给出了全并行译码器的 FPGA 实现方法。

Method of Parallel LDPC Decoder and FPGA Implementation

Low-density parity-check (LDPC) codes as one of the best performance of the error control codes, has been widely used in wireless communication, satellite communication, wireless network and many other digital communication areas. With the development of 5th generation of Tele-communication, the demand for transmission rate in communication system is increasing gradually. A method of parallel LDPC decoder and FPGA implementation are derived in this article, with theoretical analysis and simulation. The method of FPGA Implementation of parallel LDPC serially concatenated systems under different encoding algorithms are realized, and the most appropriate are chosen.