Low-Power Area-Efficient Pipelined A/D Converter Design Using a Single-Ended Amplifier |
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Authors: | Daisuke Miyazaki Shoji Kawahito |
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Affiliation: | (1) Department of Information and Computer Sciences, Toyohashi University of Technology, Toyohashi-shi, 441–8580, Japan |
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Abstract: | This paper presents a new scheme of a low-power area-efficient pipelined A/D converter using a single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient design of high-speed A/D converters. The estimated power dissipation of the 10-b pipelined A/D converter is less than 12 mW at 20 MSample/s. |
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Keywords: | pipelined A/D converter single-ended amplifier low power design portable video device |
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