| 一种高速直接数字频率合成器及其FPGA实现 |
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| 引用本文： | 唐长文,闵昊. 一种高速直接数字频率合成器及其FPGA实现[J]. 微电子学, 2001, 31(6): 451-454 |
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| 作者姓名： | 唐长文 闵昊 |
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| 作者单位： | 复旦大学专用集成电路与系统国家实验室, |
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| 摘 要： | 介绍了一种用于QAM调制和解调的直接数字频率合成器，该电路同时输出10位正弦和余弦两种波形，系统时钟频率为50MHz，信号的谐波小于－72dB。输出信号的范围为DC到25MHz，信号频率步长为0．0116Hz，相应的转换速度为20ns，建立时间延迟为4个时种。直接数字合成器（DDFS）采用一种有效查找表的方式生成正弦函数，为了降低ROM的大小，采用了1／8正弦波形函数压缩算法。直接数字频率合成器的数字部分由Xilinx FPGA实现，最后通过数模转换器输出。
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| 关 键 词： | 数字频率合成器 锁相环 现场可编程逻辑阵列 查找表 只读存储器 |
| 文章编号： | 1004-3365(2001)06-0451-04 |
| 修稿时间： | 2001-01-19 |
A Direct Digital Frequency Synthesizer Implemented with FPGA |
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| TANG Zhang wen,MIN Hao. A Direct Digital Frequency Synthesizer Implemented with FPGA[J]. Microelectronics, 2001, 31(6): 451-454 |
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| Authors: | TANG Zhang wen MIN Hao |
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| Abstract: | A direct digital frequency synthesizer (DDFS) used for QAM modulation and demodulation is presented, which synthesizes a 10 b output sine and cosine wave with a spectral purity of -70 dB at 50 MHz The synthesizer covers a bandwidth from dc to 25 MHz in 0 0116 Hz step with a corresponding switching speed of 20 ns and a tuning latency of 4 clock cycles An efficient look up table method for calculating the sine function is used, and a compressed algorithm that only calculates 1/8 sine function is employed to reduce the volume of ROM The whole digital system is implemented with Xilinx FPGA, and the digital signals are output through two D/A converters |
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| Keywords: | Digital frequency synthesizer Phase locked loop FPGA Look up table ROM |
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