| 基于FPGA的ISA总线接口逻辑设计 |
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| 引用本文： | 沈晓红,鲁延峰,李凯. 基于FPGA的ISA总线接口逻辑设计[J]. 微计算机信息, 2011, 0(7) |
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| 作者姓名： | 沈晓红 鲁延峰 李凯 |
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| 作者单位： | 北京工商大学机械工程学院; |
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| 摘 要： | 虽然各种新式总线相继出现,但ISA总线在工业领域应用相当普遍,本文提出用Verilog HDL语言写FPGA(可编程逻辑门阵列)逻辑来实现ISA总线的接口设计,可以大大减化硬件电路设计复杂的缺点,灵活简单。将设计的接口逻辑用于超声波探伤卡的ISA接口中得以验证。
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| 关 键 词： | FPGA ISA总线 Verilog HDL |
The Logical Design of ISA Bus Interface Based on FPGA |
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| SHEN Xiao-hong LU Yan-feng LI Kai. The Logical Design of ISA Bus Interface Based on FPGA[J]. Control & Automation, 2011, 0(7) |
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| Authors: | SHEN Xiao-hong LU Yan-feng LI Kai |
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| Affiliation: | SHEN Xiao-hong LU Yan-feng LI Kai (College of Mechanical Engineering,Beijing Technology and Business University,Beijing 100048,China) |
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| Abstract: | Although a variety of new bus after another, but the application of ISA bus is very common in the areas of Industry, this paper uses the Verilog HDL language to write FPGA (Field-Programmable Gate Array) logic to achieve the ISA bus interface design can be greatly simplified hardware design complexity the shortcomings of simple and flexible. The design of the interface logic for the ultrasonic testing card of the ISA interface to verify. |
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| Keywords: | FPGA ISA Bus Verilog HDL |
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