| 基于FPGA的数字下变频器设计 |
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| 引用本文： | 刘卜源,张宪,范毅军,胡云朋. 基于FPGA的数字下变频器设计[J]. 微计算机信息, 2011, 0(7) |
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| 作者姓名： | 刘卜源 张宪 范毅军 胡云朋 |
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| 作者单位： | 军事交通学院; |
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| 摘 要： | 本文设计和实现了基于FPGA的数字下变频器DDC,用于宽带数字中频软件无线电接收机中。采用自上向下的模块化设计方法,将DDC的功能划分为基本单元,实现这些功能模块并组成模块库。在具体应用时,优化配置各个模块来满足具体无线通信系统性能的要求。这样做比传统ASIC数字下变频器具有更好地可编程性和灵活性,从而满足不同的工程设计需求。
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| 关 键 词： | 数字下变频器 多相滤波 FPGA 抽取和内插 |
FPGA-based design of digital down-converter |
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| LIU Bo-yuan ZHANG Xian FAN Yi-jun HU Yun-peng. FPGA-based design of digital down-converter[J]. Control & Automation, 2011, 0(7) |
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| Authors: | LIU Bo-yuan ZHANG Xian FAN Yi-jun HU Yun-peng |
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| Affiliation: | LIU Bo-yuan ZHANG Xian FAN Yi-jun HU Yun-peng (Academy of Military Transportation,Tianjin 300161,China) |
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| Abstract: | In this paper, a digital down converter (DDC) applied on wide bandwidth digital IF receiver is design and implemented by FPGA. This DDC can translate digital IF signal to baseband, extract desired channel, decimate the sample sequence, multirate converter and channel shape. Using Top-Down design method, the whole DDC function is divided to many units implemented respectively and organized to the module library. When applying DDC on receiver, these function modules are selected, configured and optimized to a... |
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| Keywords: | Digital Down Converter Polyphase Filter FPGA Decimation and Interpolation |
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