| 基于SRAM的FPGA的互连时延模型 |
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| 引用本文： | 王怡,韩若楠,王伶俐,唐璞山,童家榕.基于SRAM的FPGA的互连时延模型[J].电路与系统学报,2008,13(3):57-62. |
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| 作者姓名： | 王怡 韩若楠 王伶俐 唐璞山 童家榕 |
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| 作者单位： | 复旦大学,专用集成电路与系统国家重点实验室,上海,201203 |
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| 基金项目： | 国家高技术研究发展计划(863计划)，国家自然科学基金，上海市AM项目 |
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| 摘 要： | 本文提出现场可编程门阵列FPGA中的互连资源MOS传输管时延模型.首先从阶跃信号推导出适合50%时延的等效电阻模型,然后在斜坡输入的时候,给出斜坡输入时的时延模型,并且给出等效电容的计算方法.结果表明,本文提出的时延模型快速并且足够精确.
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| 关 键 词： | MOS管 等效电容 MOS-C电路 |
A delay model for SRAM-based FPGA interconnections |
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| WANG Yi,HAN Ruo-nan,WANG Ling-li,TANG Pu-shan,TONG Jia-rong.A delay model for SRAM-based FPGA interconnections[J].Journal of Circuits and Systems,2008,13(3):57-62. |
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| Authors: | WANG Yi HAN Ruo-nan WANG Ling-li TANG Pu-shan TONG Jia-rong |
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| Affiliation: | WANG Yi,HAN Ruo-nan,WANG Ling-li,TANG Pu-shan,TONG Jia-rong ( ASIC & System State-Key Lab,Fudan University,Shanghai 201203,China ) |
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| Abstract: | This paper proposes FPGA interconnection pass transistor delay model. First, the equivalent resistance delay model is presented based on 50% timing delay for the pulse input. The equivalent capacitance delay model is thereafter proposed for the slope input. The corresponding effective capacitance delay calculation method is also given. The experimental results show the efficiency and accuracy of the proposed delay model for FPGA interconnection. |
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| Keywords: | MOS transistor effective capacitance |
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