基于优化电路的高性能乘法器设计

为了提高二进制乘法器的速度并降低其功耗,在乘法器的部分积产生模块采用了改进的基4Booth编码和部分积产生电路并在部分积压缩模块应用了7∶3压缩器电路,设计并实现了一种高性能的33×28二进制乘法器.在TSMC 90 nm工艺和0.9 V工作电压下,仿真结果与Synopsys公司module compiler生成的乘法器相比,部分积产生电路速度提高34%,7∶3压缩器和其他压缩器的结合使用减少了约一级全加器的延时,整体乘法器速度提高约17.7%.

High Quality Multiplier Design Based on Improved Circuits

In order to improve the speed and power consumption of the binary multiplier,this paper present a high-quality 33×28 binary multiplier with modified radix-4 Booth encoding and improved partial product circuits in partial product generator and a 7∶3 compressor in partial product compression module.Compared with the multiplier created by Synopsys′ module compiler,the speed of proposed partial product generator has improved 34%,the time of compressor has reduced about one 3∶2 compressor′s delay by combining 7∶3 compressors with other compressors and the total delay of proposed multiplier has improved 17.7% at 0.9 V on a TSMC 90 nm process technology.