Analysis and design of a new SRAM memory cell based on vertical lambda bipolar transistor

A voltage-controlled negative-differential-resistance device using a merged integrated circuit of two n-channel enhancement-mode MOSFETs and a vertical NPN bipolar transistor, called vertical Lambda-bipolar-transistor (VLBT), is presented for memory application. The new VLBT structure has been developed and its characteristics are derived by a simple circuit model and device physics. A novel single-sided SRAM cell based on the proposed VLBT is presented. Due to the characteristics of the VLBT, it offers better static noise margin and larger driving capability as compared with conventional single-side CMOS memory cell.