Optimisation of very low voltage TVS protection devices |
| |
Authors: | J Urresti S HidalgoD Flores J RoigJ Rebollo I Mazarredo |
| |
Affiliation: | a Centro Nacional de Microelectrónica (CNM-CSIC), Campus UAB, 08193 Bellaterra, Barcelona, Spain b Fagor Electrónica S.Coop., B° San Andrés, s/n-Aptdo, 33 20500, Mondragón, Guipúzcoa, Spain |
| |
Abstract: | This paper is aimed at the design and optimisation of advanced Transient Voltage Suppressors (TVS) devices for IC protection against ESD. A four-layer N+P+PN+ structure has been used to achieve breakdown voltages lower than 3 V. The effect of the critical geometrical and technological parameters on the TVS electrical characteristics is analysed with the aid of technological and electrical simulations. In this sense, the trade-off between voltage capability, leakage current and clamping voltage has been optimised. Fabricated TVS devices exhibit better electrical performances than those of the equivalent three-layer TVS device counterparts. |
| |
Keywords: | TVS Protection devices Punchthrough and clamping voltage Voltage suppressor |
本文献已被 ScienceDirect 等数据库收录! |
|