A comparative analysis and design of quantum‐dot cellular automata memory cell architecture

Quantum‐dot cellular automata (QCA) nanotechnology is considered as the best candidate for memory system owing to its dense packages and low power consumption. This paper analyzes the drawbacks of the previous QCA memory architectures and improves memory cell that exploits regular clock zone layout by employing two new clocking signals and a compact Read/Write circuit. The proposed layout is verified with the modified QCADesigner simulator and is analyzed by considering the noise effect. This design, occupying only a fraction of the area compared with the previous memory design, has superior performance. It is shown that the clock circuitry is very regular, helping manufacturability for physical implementation. Comparisons show that Read/Write latency of the proposed design is mitigated, the overall cell number, control cell and layout area are reduced (100%), and its performance against random charge noise is presented to be better. Copyright © 2010 John Wiley & Sons, Ltd.