Motion JPEG视频压缩IP核的设计与实现

设计了一个高效的全流水线结构的Motion JPEG视频压缩IP核。在设计中提出了一种适合FPGA结构的并行快速矩阵转置电路结构和全流水线的二维离散余弦变换电路结构。实验结果表明,Motion JPEG视频压缩IP核具有较大的实用价值和广阔的应用前景。

Design and application of Motion JPEG IP Core

This paper describes the design of a new structure of the entire pipeline Motion JPEG IP Core. At the design stage, we propose a highly efficient implementation of matrix transpose and dimetric discrete cosine transform. Finally, we construct a verifying system which contains NIOS II processor and Motion JPEG IP Core, based on the SoPC architecture. After testing, the Motion JPEG IP Core performs compression of NTSC in luminance component with the clock of 50Mhz in real time and processes the 952×568 continual luminance component pictures at a required operating frequency as low as 100Mhz with 147 frame/s. Therefore, it can be applied widely.