基于码密度统计的流水线模数转换器校准算法研究

本文提出了一种用于校准流水线模数转换器线性误差的数字后台校准算法。该算法不需要修改转换器级电路部分，只需要一部分用于统计模数转换器输出码的数字电路即可完成。通过分析流水线模数转换器输出的数字码，该算法可以计算出每一级级电路对应的权重。本文利用一个14位的流水线模数转换器来验证该算法。测试结果显示，转换器的积分非线性由90LSB下降到0.8LSB，微分非线性由2LSB下降到0.3LSB；信噪失真比从38dB提高到66.5dB,总谐波失真从-37dB下降到-80dB。转换器的线性度有很大提高。

A digital background calibration algorithm of a pipeline ADC based on output code calculation

This paper proposes a digital background calibration algorithm to correct linearity errors in a pipelined analog-to-digital converter (ADC). The algorithm does not modify the analog circuit of pipelined stages and calibrates the raw conversion output by using a backend digital logic. Based on the analysis of the output codes, the calibration logic estimates the bit weight of each stage and corrects the outputs. An experimental 14-bit pipelined ADC is fabricated to verify the algorithm. The results show that INL errors drop from 20 LSB to 1.7 LSB, DNL errors drop from 2 LSB to 0.4 LSB, SNDR grows from 57 to 65.7 dB and THD drops from -58 to -81 dB. The linearity of the pipelined ADC is improved significantly.