一种0.18μm数字工艺的12bit 100MS/s流水线型ADC设计

描述一个基于TSMC 0.18μm数字工艺的12 bit 100 Ms/s流水线模数转换器的设计实例。该模数转换器采用1.5bit每级结构,电源电压为1.8V。包括十级1.5 bit/stage和最后一级2bit Flash模数转换器,共产生22bit数字码,数字码经过数字校正电路产生12 bit的输出。该模数转换器省去了采样保持电路,电路模块包括:各个子流水级、共模电压生成模块、带隙基准电压生成模块、开关电容动态偏置模块、系统时钟生成模块、时间延迟对齐模块和数字校正电路模块。为了实现低功耗设计,在电路设计中综合采用了输入采样保持放大器消去、按比例缩小和动态偏置电路等技术。ADC实测结果,当以100 MHz的采样率对10MHz的正弦输入信号进行采样转换时,在其输出得到了73.23dB的SFDR,62.75dB的SNR,整体功耗仅为113mW。

A 12 bit 100 MS/s 0.18 μm Digital Technology Pipeline ADC

The design of a 12 bit 100 MS/s pipeline ADC is implemented in TSMC 0.18 μm digital CMOS technology.The ADC utilizes 1.5 bit/stage architecture with total 10 stages and one 2 bit flash ADC.The supply is 1.8 V.The digital correction circuit processes 22 bit digital codes and produces 12 bit output.Input sample and hold circuit is omitted.ADC includes sub pipeline stages,common mode voltage generator,bandgap reference voltage generator,switch-capacitor dynamic bias block,clock generator,delay module and digital correction block.To realize low power consumption,ADC,uses scales down stages and dynamic bias current block but does not include input sample and hold block.When ADC on board testing is applied a 10 MHz sinusoidal signal at 100 MHz sampling,SFDR is 73.23 dB,and SNR is over 62.75 dB.The power consumption is 113 mW.