基于FSM的时序电路测试生成探析

针对时序电路的结构特点,以有限状态机的状态转换和一致性测试分析为依据,通过采用转换故障模型来实现时序电路的功能测试生成.发现使用VHDL语言和EDA工具软件能很快实现由时序电路到有限状态机的转换,同时可得到时序电路的稳定状态及其有效可及状态.结果表明此方法可实现转换故障的测试生成,是一种研究时序电路功能测试生成的有效方法.

Discussion of Sequential Circuits Testing Method Based on Finite State Machine

Aiming at the complicated character of the sequential circuits, we use the fault model of state trasition to achieve the testing generation of the sequential circuits, which is based on state transition of the finite state machine and conference testing.The result proves that it can transform quickly from sequential circuits to finite state machine if we use the VHDL and EDA software, meanwhile,the stable state and valid reachable state of the sequential circuits can be also achieved. Therefore, we have got...