Design and optimization of BCCD in CMOS technology |
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Authors: | GAO Jing LI Yi GAO Zhi-yuan and LUO Tao |
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Affiliation: | School of Electronic Information Engineering, Tianjin University, Tianjin 300072, China;School of Electronic Information Engineering, Tianjin University, Tianjin 300072, China;School of Electronic Information Engineering, Tianjin University, Tianjin 300072, China;Tianjin Key Laboratory of Cognitive Computing and Application, School of Computer Science and Technology, Tianjin University, Tianjin 300072, China |
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Abstract: | This paper optimizes the buried channel charge-coupled device (BCCD) structure fabricated by complementary metal oxide semiconductor (CMOS) technology. The optimized BCCD has advantages of low noise, high integration and high image quality. The charge transfer process shows that interface traps, weak fringing fields and potential well between adjacent gates all cause the decrease of charge transfer efficiency (CTE). CTE and well capacity are simulated with different operating voltages and gap sizes. CTE can achieve 99.999% and the well capacity reaches up to 25 000 electrons for the gap size of 130 nm and the maximum operating voltage of 3 V. |
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